1. Field of Invention
The present invention generally relates to a method of fabricating a semiconductor device using a self-aligned silicide (Salicide) process, and more particularly to a method of fabricating a sub-quarter-micron Salicide polysilicon.
2. Description of Related Art
In accordance with advances in semiconductor process techniques, Salicide process is commonly used to form a metal silicide layer having good qualities, such as a high melting point, a high reliability and a low resistance. As IC devices are scaled down, line width of semiconductor device gates, contact areas between conductive layers, and junction depths are accordingly shrinking. The metal silicide layer is therefore formed on a polysilicon gate or a source/drain region to increase the performance of IC devices, to decrease junction resistance and to decrease RC delay which is generated from resistors and capacitors in IC devices. Therefore, driving current, response time and operation speed of IC devices increase due to the formation of the metal silicide layer.
FIGS. 1A and 1B are schematic, sequential cross-sectional diagrams showing a conventional Salicide process. As shown in FIG. 1A, a substrate 100 is provided. A MOS transistor composed of a gate 102, a spacer 104 and source/drain regions 106 is formed on the substrate 100. A metal film 108 is formed on the gate 102, the spacer 104 and source/drain regions 106. As shown in FIG. 1B, an annealing process (or a thermal process) is performed on the metal film 108 to make the metal react with the silicon that is under the metal film 108 to form a metal silicide layer 110 and 112. The metal silicide layer 110 is formed on the top surface of the gate 102 and the metal silicide layer 112 is formed on the source/drain regions 106. There is no metal silicide layer formed on other region that does not include silicon. Then the remaining metal is removed by selective wet etching. The metal silicide layer 110 and 112 are therefore exposed, as shown in FIG. 1B. As described, there is no photolithography process performing during the Salicide process.
As IC devices are scaled down even more, particularly in the deep sub-micron semiconductor techniques, sizes of semiconductor devices, contact areas between conductive layers, and junction depths are increasingly shrinking. The spacer film stress problem and the narrow line-width effect that results in limiting formation of metal silicide layer on corners 114 of the gate 102, as shown in FIG. 1B. As the area of the metal silicide layer 110 on the gate 102 decreases, the nucleation area of the metal silicide layer decreases to make it difficult to decrease of sheet resistance. The efficiency of increasing driving current, response time and operation speed of IC devices therefore is reduced.